As is well known, semiconductor manufacturing processes, as used to manufacture integrated circuits (ICs), involve a succession of fabrication operations requiring accurate registration of the tools used in each operation with respect to the semiconductor wafer being processed. More specifically, successful semiconductor manufacturing requires highly accurate alignment of features on masks used in photolithographic processes, and of their projection onto the wafer, such that successive mask-defined patterns of material are located on the wafer with accuracy in the low tens of nanometers range.
One important class of applications of the invention involves the mapping of the local "overlay" in this context, the relative location of features formed in different steps in an IC wafer fabrication process. The "overlay" is a vector quantity defined at every location on the substrate as the difference between the vector position P.sub.1 of (for example) a first-formed portion of a conductive structure on a substrate with respect to an arbitrary reference point, and the vector position of the corresponding point P.sub.2 in a second-formed portion of the structure. In the common circumstance where the first and second portions are to be directly aligned, the overlay is zero where P.sub.1 =P.sub.2, i.e., when the composite pattern is formed correctly.
It will be appreciated that overlay may thus occur in orthogonal x and y dimensions. For example, suppose an underlying conductive "trace" extending in the x direction is to be connected to an overlying trace extending in the y direction by a connecting "post" filling a through-hole or "via" formed in an intervening insulative layer. If the via is displaced in the y direction from its proper location, the connecting post will be off-center with respect to the underlying conductor, and may fail entirely to make adequate contact thereto. However, this overlay in the y-dimension may not affect the contact between the post and the orthogonal upper conductive trace. Accordingly, reference herein to overlay measured with respect to differing layers of a multiple-layer structure should be understood to include overlay of connecting elements formed in vias with respect to associated conductors, as well as overlay of the conductors per se.
For example, patterning overlay errors result when the features formed on a substrate in a second image-transfer operation are not properly located relative to features having been formed thereon in a prior operation, or when a feature is improperly located with respect to other features formed in the same imaging operation. Stated slightly differently, overlay may derive from the misalignment of images formed sequentially by the image-transfer tooling, e.g., when two or more masks are used in sequential photolithography operations to form a resulting composite pattern on the substrate, and may also result from errors or defects in one or more of the masks, e.g., improper placement of features on the masks.
The parent application, Ser. No. 08/236,202 and the application from which it claims priority (now U.S. Pat. No. 5,383,136) disclose methods and test structures useful in measuring overlay, all involving measurement of voltage drops between sections of a composite structure responsive to a current being forced therethrough. More specifically, in the grandparent application Ser. No. 07/852,439, now U.S. Pat. No. 5,383,136, a quantity "x" referred to as the "offset" was defined to be the displacement of the center tap of a potentiometer formed on a substrate in a second image-transfer operation from the midpoint between the two end taps of the potentiometer formed thereon in a prior image-transfer operation. When the offset x was zero, the composite pattern was defined to have zero-overlay. Thus the offset x measured using the potentiometer in many cases corresponded to the overlay 0 of the overlaying patterns forming the composite pattern, that is, when the overlay 0 was due entirely to the offset x. While for such potentiometers the offset x of an individual potentiometer may or may not be defined to be the same as the overlay 0 of the composite pattern, the difference between the values of x and 0 for individual composite patterns will be the same in foreseeable applications.
It is common practice in the prior art to use imaging instruments (including optical and electron microscopes, for example, in the term "imaging instruments" as used herein) to monitor various aspects of semiconductor manufacturing operations, including overlay. For example, optical instruments may be used in conjunction with substrates having a known reference grid pattern printed thereon to evaluate whether a stepper moving an optical tool across the substrate is in fact doing so accurately. It is also known to use a so-called "golden substrate" similarly having a known reference grid pattern printed thereon, and then to pattern this with a second layer of a separate material and optically measure whether the second layer of material is accurately located with respect to the grid on the golden substrate. In both cases, the accuracy of these imaging instrument measurements may be compromised by so-called "tool-induced shift" and/or "wafer-induced shift".
Generally speaking, tool-induced shift ("TIS") arises from misalignment of the imaging instrument and contributes a constant amount to the measurement of overlay (that is, misalignment of two or more separately formed features) independent of the properties of the target features. Wafer-induced shift ("WIS") arises from asymmetries in the formation of the target features that are inspected with the imaging instrument. For example, a conductive "feature" which is to be located using an imaging instrument may in theory have vertical sides meeting a flat upper surface at square corners. However, the process used to form the conductor may be such that the sides of the conductor are not parallel to one another, and thus may not meet the top of the conductor at right angles. Using an imaging instrument to measure the width of the feature, or the spacing of adjacent features formed in successive imaging operations, will result in unpredictable errors; as the severity of these errors varies with the process used to form the structure being measured, such errors are referred to as wafer-induced shift. As noted, WIS is process-dependent and varies somewhat unpredictably from one type of manufacturing process to another, although a given manufacturing process typically exhibits fairly consistent WIS.
Typically, the effects of TIS on measurements of a particular structure on a substrate can be eliminated by 180 degree rotation of the substrate about the optical axis of the instrument and averaging the measurements made with respect to the structure. While this process is generally workable, it is not popular because it requires substantial additional effort and time. WIS, however, cannot be conveniently estimated, can amount to 50 nanometers or more, can affect the impact of TIS on any given measurement, and is highly process-dependent.
Therefore, it can be seen that there is a distinct need for a method for evaluating TIS of an imaging instrument, and for evaluating WIS as measured by an imaging instrument with respect to structures formed using a particular processing sequence.
Electrical measurements, such as the voltage-drop measurements described in the predecessor applications, do not suffer from TIS; to the extent electrical measurements suffer from an electrical analog of WIS, its effect is much smaller than that exhibited by optical measurements, and in many cases can be substantially minimized, as described in the predecessor applications. Accordingly, it would be desirable to provide a test structure having features detectable by imaging instruments, and certified by electrical measurement, which could then be supplied to manufacturers or inspectors of products for calibration of imaging instruments. That is, it would be desirable to provide a structure manufactured, and tested electrically, to certify the relation of a plurality of features visible using an imaging instrument to be calibrated, this information being then provided to the user of the imaging instrument. The imaging instrument could then be calibrated accordingly. It would be further desirable to provide an electrically-testable structure which entirely eliminated any electrical analog of WIS.